Memory Management Units (MMUs) on computer systems may map a virtual address space to a physical address space. The virtual address space represents the set of logical or virtual addresses that are made available to processes. For example, the virtual address space may be divided into pages and the virtual address may be represented by a virtual page number (e.g. some most significant bits of the virtual address) and an offset within the page (e.g. the remaining least significant bits of the virtual address). MMUs may maintain a page table, which correlates virtual page numbers with physical page numbers. By looking up a page table entry using the virtual page number as an index, the MMU may obtain a corresponding physical page number, which can be combined with the offset to obtain the physical address. To speed up page table lookups, some page table entries may be cached, for example, using an associative cache. The associative cache that holds page table entries is called a translation lookaside buffer (TLB). For example, page table entries in the TLB may be updated based on prior, current or expected memory access patterns.
Modern processors often provide hardware support virtualization and/or multi-threading. Virtualization refers to the creation of a simulated environment, such as a virtual processor, for programs called “guests”. For example, a single processor core (the host) may appear as multiple processor cores to guests. The multiple processor cores are termed virtual cores or Virtual Processing Elements (VPEs). Virtualization is facilitated by a hypervisor, which provides a trusted execution environment by managing privileged resources and defining resource access and utilization policies for each guest. The hypervisor also manages memory and I/O privileges of the subsystems. Multi-threading refers to the parallel execution of code segments on a single processor core to improve overall throughput. For example, hardware resources such as processor cycles may be shared among the threads so that one thread may continue executing while another has stalled thereby improving overall utilization and throughput. The use of virtualization and/or multi-threading may facilitate efficient use of hardware resources, lower costs and decrease power consumption relative to the use of multiple physical processor cores. Therefore, some modern processors may support both virtualization and multi-threading.
However, the use of multithreading and/or virtualization often results in inefficient use of resources such as caches or TLBs, which can then become bottlenecks that degrade performance. Therefore, some disclosed embodiments present efficient techniques for TLB use in a variety of contexts.